Format synchronization in serial data links is generally obtained through the periodic insertion of sync words in the data format. Recognition of the sync word at the output of the data receiver is required in order to obtain bit level synchronization for synchronous decoding of the data.
Turning to FIG. 1, a conventional sync detector is shown for detecting an M-bit sync word within a serial input signal.
A serial data signal is clocked into an M-bit shift register 1 under control of a serial clock signal synchronized to the data signal. Successive bits appearing on the outputs of shift register 1 are compared within a correlator 2 to corresponding bits (S.sub.1, S.sub.2 . . . S.sub.M) of the M-bit sync word stored within template register 3.
The correlator 2 performs a multiplication of respective pairs of signals output from the shift register 1 and sync word template 3 via multipliers X.sub.1, X.sub.2 . . . X.sub.M. Respective outputs of the multipliers X.sub.1, X.sub.2 . . . X.sub.M are applied to the inputs of a summer 4. The output of summer 4 is applied to one input of a comparator 5, and a second input of a comparator receives a threshold signal having a value of M-T, where T designates a threshold number of acceptable errors in the received sync word.
In operation, comparator 5 generates a one bit output signal having a logic high value when the output value from summer 4 exceeds M-T, and a logic low value otherwise. In other words, if the number of agreements between the stored input data signal within shift register 1 and the sync word generated from template 3 exceeds the aforementioned threshold M-T, the sync word is considered to have been detected.
The correlator 2 may be implemented in either analog or digital form (e.g. multipliers X.sub.1, X.sub.2 . . . X.sub.M, summer 4, and comparator 5 may be either analog or digital circuits). However, the output of comparator 5 should be a binary value.
The primary limitation of the above discussed prior art sync detector is that the input data signal is processed serially, which for high data rates results in a requirement for high speed, high power and complexity of circuitry.